For the sixth-generation (6G) mobile communication, the channel coding scheme is very important. To implement high-speed low-density parity-check (LDPC) coders and decoders, Field-programmable gate arrays (FPGAs) are widely used. The well-known practice is to develop a register-transfer level (RTL) model of a digital circuit, which requires extensive simulation and system verification, resulting in a long development cycle. Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes are used to correct transmission errors in digital communication systems. Initially, ASICs were targeted due to computational complexity; many-core and multicore systems abundantly use LDPC decoders. This paper generates the code word using an 8x16 Generator Matrix derived from an 8x16 parity-check matrix. LDPC decoding is performed using hard decisions and a bit-flipping algorithm. The transceiver is modelled in MATLAB/Simulink and tested in real time on an FPGA. The FPGA board used is the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit. This board features a System-on-a-Chip (SoC) comprising an ARM processor and an FPGA. A part of the transceiver runs on the FPGA, and the rest runs on the ARM processor. Model-based design saves significant time by combining design, coding, and testing. The MATLAB/Simulink HDL Workflow advisor automatically generates code in C++ and VHDL.
