Model-based design and implementation of sdr transceiver using qc-ldpc coding-decoding over awgn channel on fpga using matlab/simulink
For the sixth-generation (6G) mobile communication, the channel coding scheme is very important. To implement high-speed low-density parity-check (LDPC) coders and decoders, Field-programmable gate arrays (FPGAs) are widely used. The well-known practice is to develop a register-transfer level (RTL) model of a digital circuit, which requires extensive simulation and system verification, resulting in a long development cycle. Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes are used to correct transmission errors in digital communication systems.